--
-- VHDL Architecture eq_lib.Freq_amp.arch
--
-- Created:
--          by - marry608.student (southfork-12.edu.isy.liu.se)
--          at - 13:41:00 10/13/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all; 

ENTITY equal IS
  PORT(
    fpga_clk    : IN    std_logic;
    fpga_reset_n: IN    std_logic;
    
    cntr_sig_enable : IN std_logic;
    cntr_sig_fin  : out std_logic;
    
    address     : out integer range 0 to 255;
    freq_re_bus_in : IN integer;
    freq_im_bus_in : IN integer;
    freq_re_bus_out : OUT integer;
    freq_im_bus_out : OUT integer;
    read_write  : BUFFER   std_logic;--0 = read
    
    band1       : BUFFER   integer;-- each bands value
    band2       : BUFFER   integer;
    band3       : BUFFER   integer;
    band4       : BUFFER   integer;
    band5       : BUFFER   integer;
    band6       : BUFFER   integer;
    
    b1_c        : IN     std_logic_vector(1 downto 0);-- increase/decrease control signal
    b2_c        : IN     std_logic_vector(1 downto 0);
    b3_c        : IN     std_logic_vector(1 downto 0);
    b4_c        : IN     std_logic_vector(1 downto 0);
    b5_c        : IN     std_logic_vector(1 downto 0);
    b6_c        : IN     std_logic_vector(1 downto 0);
    
    band1_vol   : BUFFER integer range 0 to 9; -- scale value
    band2_vol   : BUFFER integer range 0 to 9;
    band3_vol   : BUFFER integer range 0 to 9;
    band4_vol   : BUFFER integer range 0 to 9;
    band5_vol   : BUFFER integer range 0 to 9;
    band6_vol   : BUFFER integer range 0 to 9
  );
END equal ;
  
ARCHITECTURE arch OF equal IS
  signal next_pos:integer range 0 to 256;
  signal next_pos_rev : integer;
  
  signal rev_vect : std_logic_vector(7 downto 0);
  signal org_vect : std_logic_vector(7 downto 0);
  
  signal band1_temp :integer;
  signal band2_temp :integer;
  signal band3_temp :integer;
  signal band4_temp :integer;
  signal band5_temp :integer;
  signal band6_temp :integer;
BEGIN
    
  set_bands : process(fpga_clk)
    variable temp_re : integer range -8388608 to 8388607;
    variable temp_im : integer range -8388608 to 8388607;
  begin
      if rising_edge(fpga_clk) then
        cntr_sig_fin <= '0';
        if fpga_reset_n = '0' then
          band1_temp <= 0;
          band2_temp <= 0;
          band3_temp <= 0;
          band4_temp <= 0;
          band5_temp <= 0;
          band6_temp <= 0;
          next_pos <= 0;
        elsif cntr_sig_enable = '1' then      
          case next_pos_rev is
            when 0 to 3 => 
              address <= next_pos;
              temp_re := to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_re_bus_in,24))) sra band1_vol)));
              temp_im := -to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_im_bus_in,24))) sra band1_vol)));
              freq_re_bus_out <= temp_re;
              freq_im_bus_out <= temp_im;
              band1_temp <= band1_temp + temp_re*temp_re + temp_im*temp_im;
                
            when 4 to 6 => 
              address <= next_pos;
              temp_re := to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_re_bus_in,24))) sra band2_vol)));
              temp_im := -to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_im_bus_in,24))) sra band2_vol)));
              freq_re_bus_out <= temp_re;
              freq_im_bus_out <= temp_im;
              band2_temp <= band2_temp + temp_re*temp_re + temp_im*temp_im;
              
            when 7 to 13 => 
              address <= next_pos;
              temp_re := to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_re_bus_in,24))) sra band3_vol)));
              temp_im := -to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_im_bus_in,24))) sra band3_vol)));
              freq_re_bus_out <= temp_re;
              freq_im_bus_out <= temp_im;
              band3_temp <= band3_temp + temp_re*temp_re + temp_im*temp_im;
              
            when 14 to 27 => 
              address <= next_pos;
              temp_re := to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_re_bus_in,24))) sra band4_vol)));
              temp_im := -to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_im_bus_in,24))) sra band4_vol)));
              freq_re_bus_out <= temp_re;
              freq_im_bus_out <= temp_im;
              band4_temp <= band4_temp + temp_re*temp_re + temp_im*temp_im;
                
            when 28 to 56 => 
              address <= next_pos;
              temp_re := to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_re_bus_in,24))) sra band5_vol)));
              temp_im := -to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_im_bus_in,24))) sra band5_vol)));
              freq_re_bus_out <= temp_re;
              freq_im_bus_out <= temp_im;
              band5_temp <= band5_temp + temp_re*temp_re + temp_im*temp_im;
              
            when 57 to 255 => 
              address <= next_pos;
              temp_re := to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_re_bus_in,24))) sra band6_vol)));
              temp_im := -to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(freq_im_bus_in,24))) sra band6_vol)));
              freq_re_bus_out <= temp_re;
              freq_im_bus_out <= temp_im;
              band6_temp <= band6_temp + temp_re*temp_re + temp_im*temp_im;     
            when others =>     
          end case;
              
          next_pos <= next_pos+1;
          if next_pos = 256 then
            band1  <= to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(band1_temp ,24))) sra 44)));
            band2  <= to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(band2_temp ,24))) sra 43)));
            band3  <= to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(band3_temp ,24))) sra 45)));
            band4  <= to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(band4_temp ,24))) sra 46)));
            band5  <= to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(band5_temp ,24))) sra 47)));
            band6  <= to_integer(signed(to_stdlogicvector(to_bitvector(std_logic_vector(to_signed(band6_temp ,24))) sra 50)));
            
            band1_temp <= 0;
            band2_temp <= 0;
            band3_temp <= 0;
            band4_temp <= 0;
            band5_temp <= 0;
            band6_temp <= 0; 
            next_pos <= 0;
            cntr_sig_fin <= '1';
          end if;
        end if;
      end if;
  end process;
    
    modify_bands : process(fpga_clk)
    begin
      if rising_edge(fpga_clk) then
        if fpga_reset_n = '0' then
          band1_vol <= 5;
          band2_vol <= 5;
          band3_vol <= 5;
          band4_vol <= 5;
          band5_vol <= 5;
          band6_vol <= 5;
        end if;
        
        if b1_c = "01" and band1_vol < 9 then
          band1_vol <= band1_vol+1;
        elsif b1_c = "11" and band1_vol > 0 then
          band1_vol <= band1_vol-1;
        end if;
        
        if b2_c = "01" and band2_vol < 9 then
          band2_vol <= band2_vol+1;
        elsif b2_c = "11" and band2_vol > 0 then
          band2_vol <= band2_vol-1;
        end if;
        
        if b3_c = "01" and band3_vol < 9 then
          band3_vol <= band3_vol+1;
        elsif b3_c = "11" and band3_vol > 0 then
          band3_vol <= band3_vol-1;
        end if;
        
        if b4_c = "01" and band4_vol < 9 then
          band4_vol <= band4_vol+1;
        elsif b4_c = "11" and band4_vol > 0 then
          band4_vol <= band4_vol-1;
        end if;
        
        if b5_c = "01" and band5_vol < 9 then
          band5_vol <= band5_vol+1;
        elsif b5_c = "11" and band5_vol > 0 then
          band5_vol <= band5_vol-1;
        end if;
        
        if b6_c = "01" and band6_vol < 9 then
          band6_vol <= band6_vol+1;
        elsif b6_c = "11" and band6_vol > 0 then
          band6_vol <= band6_vol-1;
        end if;
      end if;
    end process;
    
    ---------------------Reverse order---------------
    org_vect <= std_logic_vector(to_unsigned(next_pos,8));
      
    rev_vect(0) <= org_vect(7);
    rev_vect(1) <= org_vect(6);
    rev_vect(2) <= org_vect(5);
    rev_vect(3) <= org_vect(4);
    rev_vect(4) <= org_vect(3);
    rev_vect(5) <= org_vect(2);
    rev_vect(6) <= org_vect(1);
    rev_vect(7) <= org_vect(0);
    
    next_pos_rev <= to_integer(unsigned(rev_vect));    

END ARCHITECTURE arch;
  
  
  
  
  
  